A memory device that includes three-dimensionally arranged memory cells is being developed. For example, a NAND memory device includes multiple stacked electrode layers, semiconductor pillars extending in the stacking direction of the multiple stacked electrode layers, and memory cells provided at the portions where the semiconductor pillars and the electrode layers cross. In a memory device having such a structure, the memory capacity can be increased by increasing the number of stacks of electrode layers. However, as the number of stacks of electrode layers is increased, the semiconductor pillars lengthen; and the read current flowing through the memory cells decreases. There are also cases where higher capacity may be obstructed because the surface area is wider for the draw-out portion for electrically connecting a drive circuit to the electrode layers that function as control gates of the memory cells.